The Viterbi algorithm is a maximum-likelihood algorithm for decoding of convolution codes used in communications such as satellite communication, cellular relay, and wireless local area networks. In this paper, efficient error detection schemes for architectures based on low-latency, low-complexity Viterbi decoders are presented. The merit of the proposed schemes is that reliability requirements, overhead tolerance, and performance degradation limits are embedded in the structures and can be adapted accordingly. This paper present variants of recomputing with encoded operands, to detect both transient and permanent faults, and signature-based schemes with compare select adder (CSA) unit. The adders used in the proposed one is a modified self checking adders (MSeCA).The instrumented decoder architecture has been subjected to extensive error detection assessments through simulations and field programmable gate array (FPGA) implementations for benchmark.