Bit wise operations are used in many applications like digital signal processing and telecom etc. By the languages of high level programming in general purpose processors has become very costlier. In this paper we have shown Reverse bit level optimization for adder trees for multiple constant multiplications for the efficient implantation of Finite Impulse Response filters. Which decreases the cost as well the time is decreased by 21% as compared with the existing system. The code for the bit level optimization written in verilog and implemented in Xilinx Spartan 3e FPGA kit.