Large number of interconnection requirement has become a major limitation to the designs using binary logic. One of the solutions for this is Multiple- Valued Logic (MVL). MVL proves to be advantageous as it reduces dynamic power dissipation, increases computational ability, data density and requires less number of interconnects. In this paper, the implementation of a Static Random Access Memory (SRAM) cell using a quaternary D Latch is proposed. The D Latch is built using NMAX, NMIN and quaternary inverter circuit. Using this SRAM cell a 4X4 SRAM array is constructed and is compared with 4X4 array of Quaternary Static CMOS memory cell. The spice coding is done using 0.18μm CMOS technology and verification of the design is done through HSPICE and COSMOSSCOPE Synopsis Tools. Power and delay of the circuit is analyzed.