Low Power consumption has become growing larger for communication systems and battery operated devices. These are laptop computers, multimedia products, and cell phones. For this battery operated devices, the energy consumption is a critical issue for design since it affect the batteries life. Thereby, the reduction of the energy consumption is become one of the most growing topics in the electronics industry and it is the most challenging areas of research. In the present time, modern design and technologies external testing become more difficult. Therefor built-in self-test has to rise as a sign of future excellence solution to the testing problem. BIST is a design for testability methodology to find out faulty elements in a system by incorporate test logic on-chip. A modern low power test pattern generator is using a linear feedback shift register (LFSR), called LP-TPG, is presented to reduce the average and peak power of a digital circuit during test. The test patterns generated by LP-TPG are more than conventional LFSR. The objective of having intermediate patterns is to reduce the internal activities of primary inputs which decrease the switching activities in the circuit under test (CUT), and power consume. The irregular nature of the test patterns is holding on perfect. The area over the additional components to the LFSR is significant compared to the large circuit sizes. The experimental results are shown verify up to 63% and 20% reduction in average and peak power, respectively.